This invention relates to a PLL (Phase Locked Loop) circuit and an optical communication reception apparatus, and more particularly to a PLL circuit which includes a phase detection circuit and a frequency detection circuit and an optical communication reception apparatus which uses a PLL circuit as a production circuit for a clock signal to be used for retiming processing of received data.
FIG. 14 shows a configuration of a PLL circuit which is used commonly. Referring to FIG. 14, the PLL circuit shown includes a phase detection (PD) circuit 101 and a frequency detection (FD) circuit 102 and operates in the following manner.
First, the frequency detection circuit 102 performs phase comparison between an input signal DATA and clock signals (ICLK, QCLK). Then, the frequency of a frequency clock VCOCLK of a voltage-controlled oscillator (VCO) 106 is controlled through a charge pump (CP) circuit 104 and a loop filter 105 based on a result of the comparison to pull the oscillation frequency of the VCO 106 to a target oscillation frequency. The clock signals (ICLK, QCLK) are produced based on the oscillation frequency clock VCOCLK of the VCO 106 by a clock generator 107.
Then, the phase detection circuit 101 performs phase comparison between the input signal DATA and the oscillation frequency clock VCOCLK of the VCO 106. Then, the phase detection circuit 101 controls the phase of the frequency clock VCOCLK of the VCO 106 through another charge pump circuit 103 and the loop filter 105 based on a result of the comparison to cause the phase of the frequency clock VCOCLK of the VCO 106 with the phase of the input signal DATA
In a PLL circuit of the type described, a frequency comparison circuit of such a configuration as shown in FIG. 15 is conventionally used for the frequency detection circuit 102. In the following, a detailed circuit configuration and operation of the frequency detection circuit 102 are described.
It is assumed here that the digital signal DATA inputted to the frequency detection circuit 102 has a non-return-to-zero (NRZ) waveform. It is also assumed that the clock generator 107 divides the oscillation frequency clock VCOCLK of the VCO 106 to a predetermined dividing ratio 1/n (in the example described, n=1) to produce the clock signal ICLK and shifts the phase of the clock signal ICLK by 90 degrees to produce the clock signal QCLK, and the clock signals ICLK and QCLK are inputted to the frequency detection circuit 102.
First, a data input terminal 111 to which the input signal DATA of an NRZ waveform is linked is connected to the D (data) input terminal of a D-type flip-flop (D-FF) 112 and connected also to an input terminal A of an exclusive OR (EX-OR) gate 113. Meanwhile, an ICLK input terminal 114 to which the clock signal ICLK is inputted is connected to an input terminal A of each of a pair of AND gates 116 and 117 while a QCLK input terminal 115 to which the clock signal QCLK is inputted is connected to the other input terminals B of the AND gates 116 and 117. The input terminal A of the AND gate 117 is a negated input terminal through which the clock signal ICLK is inputted with the reversed polarity.
The output terminals of the AND gates 116 and 117 are connected to the D input terminals of D-FFs 118 and 119, respectively. The output terminal of the EX-OR gate 113 is connected to the CLK input terminals of the D-FFs 118 and 119. The Q output terminals of the D-FFs 118 and 119 are connected to the D input terminals of D-FFs 120 and 121, and the Q output terminals of the D-FFs 120 and 121 are connected to the D input terminals of D-FFs 122 and 123, respectively. The CLK terminals of the D-FF 112 and the D-FFs 120 to 123 are connected to the ICLK input terminal 114.
The Q output terminal of the D-FF 122 is connected to an input terminal A of an AND gate 124. The Q output terminal of the D-FF 123 is connected to an input terminal B of another AND gate 125. The Q output terminal of the D-FF 120 is further connected to an input terminal A of the AND gate 125, and the Q output terminal of the D-FF 121 is connected to an input terminal B of the AND gate 124. The output terminals of the AND gates 124 and 125 are connected to circuit output terminals 126 and 127, respectively.
A DOWN pulse signal for controlling the VCO 106 of FIG. 14 to lower the oscillation frequency of it is extracted as an output signal from the AND gate 124 while an UP pulse signal for controlling the VCO 106 to raise the oscillation frequency is extracted as an output signal from the AND gate 125. The DOWN pulse signal and the UP pulse signal are supplied to the charge pump circuit 104 of FIG. 14 through the circuit output terminals 126 and 127, respectively.
Now, circuit operation of the frequency detection circuit having the configuration described above is described with reference to a timing chart of FIG. 16. In FIG. 16, waveforms (a) to (o) indicate waveforms at nodes (a) to (o) of FIG. 15, respectively.
First, the clock signal ICLK (a) has a pulse waveform wherein it rises to the xe2x80x9cHxe2x80x9d (high) level at time t0 and falls to the xe2x80x9cLxe2x80x9d (low) level at time t2. Similarly, the clock signal ICLK (a) rises at times t4, t8, t12, . . . and falls at times t6, t10, . . . The clock signal ICLK (a) is supplied to the input terminals A of the AND gates 116 and 117 through the ICLK input terminal 114 and supplied also to the CLK terminals of the D-FF 112 and the D-FFs 120 to 123.
The clock signal QCLK (b) has a pulse waveform having a phase shifted by 90 degrees, more particularly, delayed by 90 degrees with respect to the clock signal ICLK (a). In particular, the clock signal QCLK (b) rises to the xe2x80x9cHxe2x80x9d level at times t1, t5, t9, . . . and falls to the xe2x80x9cLxe2x80x9d level at times t3, t7, t11, . . . The clock signal QCLK (b) is supplied to the input terminals B of the AND gates 116 and 117.
The AND gate 116 logically ANDs the clock signal ICLK (a) and the clock signal QCLK (b). Therefore, the output signal (c) of the AND gate 116 exhibits the xe2x80x9cHxe2x80x9d level within those periods within which both of the clock signals ICLK and QCLK have the xe2x80x9cHxe2x80x9d level, that is, within the period from time t1 to time t2, the period from time t5 to time t6 and the period from time t9 to time t10. Within the other periods, that is, within the period from time t0 to time t1, the period from time t2 to time t5, the period from time t6 to time t9 and the period from time t10 to time t12, the output signal (c) of the AND gate 116 exhibits the xe2x80x9cLxe2x80x9d level.
Meanwhile, the AND gate 117 logically ANDs the inverted clock signal ICLKX of the clock signal ICLK (a) and the clock signal QCLK (b). Therefore, the output signal (d) of the AND gate 117 exhibits the xe2x80x9cHxe2x80x9d level within those periods within which both of the clock signals ICLKX and QCLK have the xe2x80x9cHxe2x80x9d level, that is, within the period from time t2 to time t3, the period from time t6 to time t7 and the period from time t10 to time t11. Within the other periods, that is, within the period from time t0 to time t2, the period from time t3 to time t6, the period from time t7 to time t10 and the period later than time t11, the output signal (d) of the AND gate 117 exhibits the xe2x80x9cLxe2x80x9d level.
In the timing chart of FIG. 16, the period within which the output signal (c) exhibits the xe2x80x9cHxe2x80x9d level is represented as a period A while the period within which the output signal (d) exhibits the xe2x80x9cHxe2x80x9d level is represented as a period B.
Meanwhile, the NRZ input signal DATA (f) is supplied immediately to the input terminal A of the EX-OR gate 113 through the data input terminal 111 and supplied also to the D input terminal of the D-FF 112. The D-FF 112 fetches the xe2x80x9cHxe2x80x9d level xe2x80x9cLxe2x80x9d level of the input waveform to the D input terminal at the timing of a rising edge of the clock signal ICLK (a). In this instance, if the input signal DATA (f) has the xe2x80x9cHxe2x80x9d level at time t0, then since the D-FF 112 fetches this, the level of the Q output signal (e) thereof changes to the xe2x80x9cHxe2x80x9d level.
Then, since the input signal DATA (f) changes between times t1 and t2 and reverses its polarity, the D-FF 112 fetches the input signal DATA (f) of the xe2x80x9cLxe2x80x9d level and changes its Q output signal (e) to the xe2x80x9cLxe2x80x9d level at the timing of a next rising edge of the clock signal ICLK (a). Further, since the polarity of the input signal DATA (f) reverses again between times t6 and t7, the D-FF 112 fetches the input signal DATA (f) of the xe2x80x9cHxe2x80x9d level at the next rising timing t8 of the clock signal ICLK (a) and changes its Q output signal (e) to the xe2x80x9cHxe2x80x9d level. Thereafter, the D-FF 112 keeps the xe2x80x9cHxe2x80x9d level till time t12.
The Q output signal (e) of the D-FF 112 is supplied to the input terminal B of the EX-OR gate 113. The EX-OR gate 113 exclusively ORs the Q output signal (e) supplied to the input terminal B and the input signal DATA (f) supplied to the input terminal A. As a result, as can be seen from the timing chart of FIG. 16, the level of the output signal (g) of the EX-OR gate 113 changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level when the input signal DATA (f) reverses during the period from time t1 to time t2, and changes back to the xe2x80x9cLxe2x80x9d level at time t4 at which the Q output signal (e) of the D-FF 112 exhibits a level change to the xe2x80x9cLxe2x80x9d level.
For the period after time t4 till a next data reversal of the input signal DATA (f), the output signal (g) of the EX-OR gate 113 maintains the xe2x80x9cLxe2x80x9d level. Then, when the input signal DATA (f) reverses within the period from time t6 to time t7, the output signal (g) of the EX-OR gate 113 exhibits a level change from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level at the timing of the reversal.
Thereafter, at time t8, the level of the Q output signal (e) of the D-FF 112 changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level. Consequently, the EX-OR gate 113 logically ORs the xe2x80x9cHxe2x80x9d level of the input signal DATA (f) and the xe2x80x9cHxe2x80x9d level of the Q output signal (e), and therefore, the level of the output signal (g) of the EX-OR gate 113 changes to the xe2x80x9cLxe2x80x9d level. Then, within the following period from time t8 to time t12, the level of the output signal (g) of the EX-OR gate 113 does not exhibit a change.
The output signals (c) and (d) of the AND gates 116 and 117 are inputted to the D input terminals of the D-FFs 118 and 119 in the next stage, respectively. The D-FFs 118 and 119 receive the output signal (g) of the EX-OR gate 113 as inputs to the CLK terminals thereof, and fetch the D input waveforms at the timing of a rising edge of the clock waveform and output the fetched levels as the Q output signals (h) and (k), respectively.
Since the output signal (g) of the EX-OR gate 113 rises within the period from time t1 to time t2 and, within the period, the output signal (c) of the AND gate 116 has the xe2x80x9cHxe2x80x9d level and the output signal (d) of the AND gate 117 has the xe2x80x9cLxe2x80x9d level, the Q output signal (h) of the D-FF 118 exhibits the xe2x80x9cHxe2x80x9d level and the Q output signal (k) of the D-FF 119 exhibits the xe2x80x9cLxe2x80x9d level.
The timing at which the level of the output signal (g) of the EX-OR gate 113 changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level is a changing point of the input signal DATA (f) within the period from time t6 to time t7. Since the output signal (c) of the AND gate 116 has the xe2x80x9cLxe2x80x9d level and the output signal (d) of the AND gate 117 has the xe2x80x9cHxe2x80x9d level at the timing, the level of the Q output signal (h) of the D-FF 118 changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level and the level of the Q output signal (k) of the D-FF 119 changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level. Thereafter, the levels are maintained till time t12.
The Q output signals (h) and (k) of the D-FFs 118 and 119 are supplied to the D input terminals of the D-FFs 120 and 121, respectively. The D-FFs 120 and 121 receive the clock signal ICLK (a) as the CLK inputs thereto and fetch the D input waveforms at the timing of a rising edge of the waveform of the clock signal ICLK (a). Here, the timing of the rising edge of the clock signal ICLK (a) is time t4, and since the Q output signal (h) of the D-FF 118 has the xe2x80x9cHxe2x80x9d level and the Q output signal (k) of the D-FF 119 has the xe2x80x9cLxe2x80x9d level at the timing, the level of the Q output signal (i) of the D-FF 120 becomes the xe2x80x9cHxe2x80x9d level and the level of the Q output signal (1) of the D-FF 121 becomes the xe2x80x9cLxe2x80x9d level.
The next rising edge timing of the clock signal ICLK (a) is time t8 and the Q output signal (h) of the D-FF 118 has the xe2x80x9cLxe2x80x9d level then. Therefore, the level of the Q output signal (i) of the D-FF 120 changes to the xe2x80x9cLxe2x80x9d level. Meanwhile, since the level of the Q output signal (k) of the D-FF 119 is the xe2x80x9cHxe2x80x9d level, the level of the Q output signal (1) of the D-FF 121 changes to the xe2x80x9cHxe2x80x9d level. The levels of the Q output signals (i) and (1) are maintained till time t12.
The Q output signals (i) and (1) of the D-FFs 120 and 121 are inputted to the D input terminals of the D-FFs 122 and 123 in the next stage, respectively. Also the D-FFs 122 and 123 receive the clock signal ICLK (a) as the CLK inputs thereto and fetch the D input waveforms at the timing of a rising edge of the waveform. Here, the rising edge timing of the clock signal ICLK (a) is time t8 and the D-FFs 122 and 123 fetch the levels of the Q output signals (i) and (1) of the D-FFs 120 and 121, respectively. Consequently, the level of the Q output signal (j) of the D-FF 122 changes to the xe2x80x9cHxe2x80x9d level and the level of the Q output signal (m) of the D-FF 123 changes to the xe2x80x9cLxe2x80x9d level.
The timing at which the clock signal ICLK (a) rises subsequently is time t12, and the Q output signal (i) of the D-FF 120 has the xe2x80x9cLxe2x80x9d level and the Q output signal (1) of the D-FF 121 has the xe2x80x9cHxe2x80x9d level at the timing. Therefore, the level of the Q output signal (j) of the D-FF 122 changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level while the level of the Q output signal (m) of the D-FF 123 changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level.
The Q output signal (j) of the D-FF 122 is supplied to the input terminal A of the AND gate 124. The Q output signal (1) of the D-FF 121 is supplied to the input terminal B of the AND gate 124. Consequently, the level of the DOWN pulse signal which is the output signal (n) of the AND gate 124 changes to the xe2x80x9cLxe2x80x9d level because the Q output signal (1) of the D-FF 121 changes to the xe2x80x9cLxe2x80x9d level at time t4. Then, at time t8, since both of the levels of the Q output signals (1) and (j) of the D-FFs 121 and 122 change to the xe2x80x9cHxe2x80x9d level, the level of the DOWN pulse signal changes to the xe2x80x9cHxe2x80x9d level.
Then at time t12, since the level of the Q output signal (1) of the D-FF 121 does not change and remains at the xe2x80x9cHxe2x80x9d level, the level of the Q output signal (j) of the D-FF 122 changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level. Accordingly, the level of the output signal (n) of the AND gate 124, that is, the level of the DOWN pulse signal, changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level.
Meanwhile, the Q output signal (m) of the D-FF 123 is supplied to the input terminal B of the AND gate 125. The Q output signal (i) of the D-FF 120 is supplied to the input terminal A of the AND gate 125. Consequently, the UP pulse signal which is the output signal (o) of the AND gate 125 exhibits the xe2x80x9cLxe2x80x9d level because the levels of the Q output signals (i) and (m) of the D-FFs 120 and 123 change to the xe2x80x9cLxe2x80x9d level at time t8. Then at time t12, the level of the Q output signal (m) of the D-FF 123 changes to the xe2x80x9cHxe2x80x9d level. However, since the level of the Q output signal (i) of the D-FF 120 remains at the xe2x80x9cLxe2x80x9d level, the output signal (o) of the AND gate 125 maintains the xe2x80x9cLxe2x80x9d level.
From the foregoing, the frequency detection circuit of FIG. 15 generally operates in the following manner. If (ICLK, QCLK)=(0, 1) are sampled at a certain DATA changing point of time and then (ICLK, QCLK)=(1, 1) are sampled at the next DATA changing point of time, then an UP pulse signal of a duration equal to one period of the clock signal ICLK is outputted. In particular, if data of m bits (m is an arbitrary integer) is present between the two DATA changing points of time, then since this signifies that less than m cycles of the clock signal ICLK are present within the period, in order to raise the frequency of the clock signal ICLK, a pulse or pulses of the UP pulse signal are produced.
On the other hand, if (ICLK, QCLK)=(0, 1) are sampled at a certain DATA changing point of time and then (ICLK, QCLK)=(0, 0) are sampled at the next DATA changing point of time, then a DOWN pulse signal of a duration equal to one period of the clock signal ICLK is generated. Thus, if data of mxe2x80x2 bits (mxe2x80x2 is an arbitrary integer) is present between the two DATA changing points of time, this signifies that more than mxe2x80x2 cycles of the clock signal ICLK are present within the period, and in order to lower the frequency of the clock signal ICLK, a pulse or pulses of the DOWN pulse signal are produced.
When the frequencies of the clock signal ICLK and the input signal DATA fully coincide with each other, one of (0, 0), (0, 1), (1, 0) and (1, 1) is successively sampled at each DATA changing point of time, and no pulse of the UP pulse signal or the DOWN pulse signal is generated.
In this manner, the output signal (n) of the AND gate 124 is supplied as the DOWN pulse signal and the output signal (o) of the AND gate 125 is supplied as the UP pulse signal to the charge pump circuit 104 of the charge pump circuit 104. Then, the DOWN/UP pulse signal is used to control the charge pump circuit 104 to smooth (rectify) the output current of the charge pump circuit 104 to generate a control voltage for the VCO 106 through the loop filter 105.
The operation of the frequency detection circuit 102 in the foregoing description relates to operation when the duty ratios of the input signal DATA and the clock signals (ICLK and QCLK) are 100% and 50%, respectively. However, particularly in optical communication of the like, the transmission signal DATA suffers from some duty distortion as seen from the waveform (b) or (c) of FIG. 17, and this may possibly give rise to malfunction of the PLL circuit. FIG. 18 illustrates waveforms of the clock signals ICLK and QCLK and the transmission signal DATA when they suffer from some duty distortion.
As described hereinabove, in the conventional frequency detection circuit, the values of the clock signal ICLK and the clock signal QCLK are sampled at a changing point of time of the input signal DATA. Therefore, if the frequencies of the signals coincide fully with each other, then the sample value within the period from time t2 to time t3 in FIG. 16 is xe2x80x9c0xe2x80x9d for the clock signal ICLK and xe2x80x9c1xe2x80x9d for the clock signal QCLK; the sample value within the period from the next DATA changing point t6 to time t7 is xe2x80x9c0xe2x80x9d for the clock signal ICLK and xe2x80x9c0xe2x80x9d for the clock signal QCLK; and if a DATA changing point is present within the period from time t10 to time t11, then the sample value at the point of time is xe2x80x9c0xe2x80x9d for the clock signal ICLK and xe2x80x9c1xe2x80x9d for the clock signal QCLK. Thus, it can be seen that the sample values at the three changing points are equal to one another.
However, as can be seen from the timing chart of FIG. 18 which illustrates a timing relationship when the input signal DATA is distorted and has a different duty ratio, whereas the clock signal QCLK is obtained by delaying the phase of the clock signal ICLK by 90 degrees, if the duty ratio of the input signal DATA increases and the width for one bit of the xe2x80x9cHxe2x80x9d level thereof becomes greater than the period of the clock signal ICLK, then if the input signal DATA rises within the period from time t1 to time t2, then the level of the clock signal ICLK is xe2x80x9c1xe2x80x9d and the level of the clock signal QCLK is xe2x80x9c1xe2x80x9d at the rising edge of the input signal DATA.
Then, when the input signal DATA exhibits a falling edge within the period from time t7 to time t8, both of the levels of the clock signal ICLK and the clock signal QCLK exhibit xe2x80x9c0xe2x80x9d, and the sample values of the clock signals ICLK and QCLK at the rising edge and the falling edge of the input signal DATA exhibit a variation from (1, 1) to (0, 0). Consequently, the frequency detection circuit malfunctions apparently.
On the other hand, if the duty ratio of the input signal DATA decreases and the width of one bit of the xe2x80x9cHxe2x80x9d level thereof becomes smaller than the period of the clock signal ICLK, then both of the levels of the clock signals ICLK and QCLK exhibit xe2x80x9c0xe2x80x9d at a rising edge of the input signal DATA within the period from time t3 to time t4. However, both of the levels of the clock signals ICLK and QCLK exhibit xe2x80x9c1xe2x80x9d at a falling edge of the input signal DATA within the period from time t5 to time t6. Consequently, the sample values of the clock signals ICLK and QCLK exhibit a change from (0, 0) to (1, 1). As a result, the frequency detection circuit malfunctions apparently.
Now, a general configuration of the phase detection circuit 101 is described. FIG. 19 shows an example of a circuit configuration of the phase detection circuit 101.
Referring to FIG. 19, a data input terminal 131 to which the input signal DATA is supplied is connected to the D input terminal of a D-FF 133 and connected also to an input terminal A of a 2-input exclusive OR (EX-OR) gate 135. Meanwhile, a CLK input terminal 132 to which the oscillation frequency clock VCOCLK of the VCO 106 is linked is connected to the CLK terminal of a D-FF 133 and connected also to a negated CLK terminal of a D-FF 134.
The Q output terminal of the D-FF 133 is connected to the other input terminal B of the EX-OR gate 135, an input terminal A of a 2-input EX-OR gate 136, and the D input terminal of the D-FF 134. The Q output terminal of the D-FF 134 is connected to the other input terminal B of the EX-OR gate 136. The output terminal of the EX-OR gate 135 is connected to an UP output terminal 137 while the output terminal of the EX-OR gate 136 is connected to a DOWN output terminal 138.
Now, circuit operation of the phase detection circuit 101 having the configuration described above is described with reference to a timing chart of FIG. 20. It is to be noted that, in FIG. 20, waveforms (a) to (f) represent waveforms at nodes (a) to (f) of FIG. 19, respectively.
It is assumed now that the oscillation frequency clock VCOCLK (a) inputted from the VCO 106 (refer to FIG. 14) through the CLK input terminal 132 rises at times t0, t2, t4, t6, t8, t10, t12 and t14 an falls at times t1, t3, t5, t7, t9, t11, t13 and t15.
Also it is assumed that the waveform of the input signal DATA (b) falls between times t1 and t2 and rises between times t5 and t6 and thus keeps the xe2x80x9cLxe2x80x9d level within the period between the falling and rising edges; it falls between times t8 and t9 and keeps the xe2x80x9cHxe2x80x9d level within the period between the preceding rising edge and the falling edge, it rises between times t10 and t11 and keeps the xe2x80x9cLxe2x80x9d level within the period between the preceding falling edge and the rising edge; it falls between times t12 and t13 and keeps the xe2x80x9cHxe2x80x9d level within the period between the preceding rising edge and the falling edge; and it thereafter keeps the xe2x80x9cLxe2x80x9d level till time t15.
The D-FF 133 fetches the xe2x80x9cLxe2x80x9d level of the input signal DATA (b) at the rising timing t2 of the oscillation frequency clock VCOCLK (a). Consequently, the level of the Q output signal (c) of the D-FF 133 changes to the xe2x80x9cLxe2x80x9d level. At the next rising timing t4 of the oscillation frequency clock VCOCLK (a), the input signal DATA does not exhibit a change and remains in the xe2x80x9cLxe2x80x9d level, and therefore, also the Q output signal (c) of the D-FF 133 does not exhibit a change but maintains the xe2x80x9cLxe2x80x9d level.
Since the input signal DATA has the xe2x80x9cHxe2x80x9d level at the next rising timing t6 of the oscillation frequency clock VCOCLK (a), the level of the Q output signal (c) of the D-FF 133 changes to the xe2x80x9cHxe2x80x9d level. Further, at the rising timing of the oscillation frequency clock VCOCLK (a) at time t8, the input signal DATA has the xe2x80x9cHxe2x80x9d level, and since the D-FF 133 fetches the xe2x80x9cHxe2x80x9d level of the input signal DATA, the Q output signal (c) of the D-FF 133 does not exhibit a change but remains in the xe2x80x9cHxe2x80x9d level.
Since, at time t10, the level of the input signal DATA has the xe2x80x9cLxe2x80x9d level, the level of the Q output signal (c) of the D-FF 133 changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level. Since, at time t12, the level of the input signal DATA has the xe2x80x9cHxe2x80x9d level, the level of the Q output signal (c) of the D-FF 133 changes to the xe2x80x9cHxe2x80x9d level, and then at time the next rising timing t14 of the oscillation frequency clock VCOCLK (a), the input signal DATA has the xe2x80x9cLxe2x80x9d level. Consequently, the D-FF 133 fetches the xe2x80x9cLxe2x80x9d level of the input signal DATA, and the level of the Q output signal (c) of the D-FF 133 changes to the xe2x80x9cLxe2x80x9d level.
Meanwhile, the oscillation frequency clock VCOCLK (a) is supplied in an inverted form as a CLK input to the D-FF 134. Accordingly, the D-FF 134 fetches the input signal DATA at times t1, t3, t5, t7, t9, t11, t13 and t15 at which the oscillation frequency clock VCOCLK (a) falls.
At time t1, since the Q output signal (c) of the D-FF 133 has the xe2x80x9cHxe2x80x9d level, the level of the Q output signal (d) of the D-FF 134 changes to the xe2x80x9cHxe2x80x9d level, and the xe2x80x9cHxe2x80x9d level is maintained till the next falling timing t3 of the oscillation frequency clock VCOCLK (a). At time t3, since the Q output signal (c) of the D-FF 133 has the xe2x80x9cLxe2x80x9d level, the D-FF 134 fetches the xe2x80x9cLxe2x80x9d level and the level of the Q output signal (d) thereof changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level. Then, the Q output signal (d) maintains the xe2x80x9cLxe2x80x9d level till immediately before time t7 past time t5.
At the falling timing of the oscillation frequency clock VCOCLK (a) at time t7, since the Q output signal (c) of the D-FF 133 has the xe2x80x9cHxe2x80x9d level, the D-FF 134 fetches the xe2x80x9cHxe2x80x9d level, and consequently, the level of the Q output signal (d) of the D-FF 134 changes to the xe2x80x9cHxe2x80x9d level. The level of the Q output signal (c) of the D-FF 133 does not change at time t9 but changes to the xe2x80x9cLxe2x80x9d level at time t10, and maintains the xe2x80x9cLxe2x80x9d level till time t12. At time t11, the Q output signal (c) of the D-FF 133 has the xe2x80x9cLxe2x80x9d level, and the D-FF 134 fetches the xe2x80x9cLxe2x80x9d level. Therefore, the Q output signal (d) of the D-FF 134 changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level.
At time t13, since the Q output signal (c) of the D-FF 133 has the xe2x80x9cHxe2x80x9d level, the D-FF 134 fetches the xe2x80x9cHxe2x80x9d level and the level of the Q output signal (d) of the D-FF 134 changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level. The information of the xe2x80x9cHxe2x80x9d level is maintained till the next falling timing t15 of the oscillation frequency clock VCOCLK (a), at which the xe2x80x9cLxe2x80x9d level of the Q output signal (c) of the D-FF 133 is fetched into the D-FF 134. Consequently, the level of the Q output signal (d) of the D-FF 134 changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level.
Now, operation of the EX-OR gate 135 which generates the UP pulse signal (e) is described with reference to a timing chart of FIG. 20. It is to be noted that the input signal DATA (b) and the Q output signal (c) of the D-FF 133 are supplied to the two input terminals A and B of the EX-OR gate 135.
The logical values of the input signal DATA (b) and the Q output signal (c) of the D-FF 133 are different from each other within the period from a point of time at which the level of the input signal DATA (b) changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level between times t1 and t2 to time t2 at which the Q output signal (c) of the D-FF 133 has the xe2x80x9cHxe2x80x9d level, within the period from a point of time at which the level of the input signal DATA (b) changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level between times t5 and t6 to time t6 at which the level of the Q output signal (c) of the D-FF 133 changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level, within the period from a point of time at which the level of the input signal DATA (b) changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level between times t8 and t9 to time t10, within the period from a point of time at which the level of the input signal DATA (b) changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level between times t10 and t11 to time t12, and within the period from a point of time at which the level of the input signal DATA (b) changes from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level between times t12 and t13 to time t14.
Within the periods specified above, the output signal (e) of the EX-OR gate 135 exhibits the xe2x80x9cHxe2x80x9d level. Within other periods, since both of the signal levels of the input signal DATA (b) and the Q output signal (c) of the D-FF 133 have either the xe2x80x9cHxe2x80x9d level or the xe2x80x9cLxe2x80x9d level, the output signal (e) of the 2-input EX-OR gate 135 exhibits the xe2x80x9cLxe2x80x9d level and is used as the UP pulse signal.
Now, operation of the EX-OR gate 136 which generates the DOWN pulse signal (f) is described with reference to the timing chart of FIG. 20. It is to be noted that the Q output signal (c) of the D-FF 133 and the Q output signal (d) of the D-FF 134 are supplied to the two input terminals A and B of the EX-OR gate 136, respectively.
The logical values of the Q output signal (c) of the D-FF 133 and the Q output signal (d) of the D-FF 134 are different from each other within the period from time t2 to time t3, the period from time t6 to time t7, the period from time t10 to time t11, the period from time t12 to time t13 and the period from time t14 to time t15.
Within the periods, the DOWN pulse signal (f) of the EX-OR gate 136 exhibits the xe2x80x9cHxe2x80x9d level. Within other periods, since both of the signal levels of the Q output signal (c) of the D-FF 133 and the Q output signal (d) of the D-FF 134 have either the xe2x80x9cHxe2x80x9d level or the xe2x80x9cLxe2x80x9d level, the DOWN pulse signal (f) of the EX-OR gate 136 exhibits the xe2x80x9cLxe2x80x9d level and is used as the DOWN pulse signal.
In this manner, each time the level of the input signal DATA changes, the pulse waveforms of the UP pulse signal (e) and the DOWN pulse signal (f) are generated each by one time. In the circuit example described, the pulse width of the DOWN pulse signal (f) is normally fixed, and phase control is performed by adjusting the pulse width of the UP pulse signal (e).
If the input signal DATA has no duty distortion, then if the oscillation frequency clock VCOCLK of the VCO 106 is locked to the input signal DATA by control based on the control signals (UP pulse signal/DOWN pulse signal) of the frequency detection circuit 102 and the phase detection circuit 101, then the rising timing of the clock signal ICLK is positioned at the center of the eye pattern of the input signal DATA as seen from the timing chart of FIG. 21.
As described hereinabove, the frequency detection circuit 102 samples the values (levels) of the clock signal ICLK and the clock signal QCLK at each changing point of the input signal DATA and uses the sample value to obtain frequency information. Here, if the clock signal ICLK and the input signal DATA have such a phase relationship with each other as seen in FIG. 21, then a falling timing of the clock signal ICLK and a changing point of the input signal DATA become substantially the same point of time.
Consequently, the sample value of the clock signal ICLK at a changing point of the input signal DATA by the frequency detection circuit 102 with respect to a change of the duty ratio of the input signal DATA becomes unstable (however, the sample value of the clock signal QCLK is stable when compared with that of the clock signal ICLK). At this time, the frequency detection circuit 102 detects the frequency information but in error and generates a wrong control signal.
As described above, in the conventional PLL circuit which includes the phase detection circuit 101 and the frequency detection circuit 102, since the frequency detection circuit 102 samples the clock signal ICLK and the clock signal QCLK at each changing point of the input signal DATA, when the input signal DATA has some duty distortion, a wrong control signal (UP pulse signal/DOWN pulse signal) is outputted from the frequency detection circuit 102.
Further, when the frequency clock VCOCLK of the VCO 106 is locked to the input signal DATA, since the center of the eye pattern of the input signal DATA is positioned at a rising edge of the clock signal ICLK by action of the phase detection circuit 101, the sample value of the clock signal ICLK by the frequency detection circuit 102 with respect to a small change of the duty ratio of the input signal DATA becomes unstable, and a wrong control signal is outputted from the frequency detection circuit 102.
It is an object of the present invention to provide a PLL circuit and an optical communication reception apparatus wherein, even if the duty ratio of an input signal varies, the convergence time required for frequency detection of a frequency detection circuit is short and wrong operation of the frequency detection circuit with a control signal is less likely to occur.
In order to attain the object described above, according to an aspect of the present invention, there is provided a PLL circuit, comprising an oscillator for generating an oscillation frequency signal having a variable oscillation frequency, a signal generation circuit for generating, based on the oscillation frequency signal of the oscillator, a first signal having a phase same as that of the oscillation frequency signal, a second signal having a fixed phase difference from the first signal, and a third signal having a phase difference smaller than the phase difference between the first and second signals from the first signal, a phase detection circuit for comparing the phases of the third signal generated by the signal generation circuit and an input signal and outputting, based on a result of the comparison, a first phase control signal for advancing the phase of the oscillation frequency signal of the oscillator or a second phase control signal for delaying the phase of the oscillation frequency signal of the oscillator, and a frequency detection circuit for fetching the first and second signals generated by the signal generation circuit in synchronism with the input signal and outputting, based on the fetched signals, a first frequency control signal for raising the frequency of the oscillation frequency signal of the oscillator or a second frequency control signal for lowering the frequency of the oscillation frequency signal of the oscillator.
According to another aspect of the present invention, there is provided an optical communication reception apparatus, comprising light reception means for receiving an optical signal, converting the optical signal into an electric signal and outputting the electric signal, a PLL circuit for producing a clock signal synchronized with the output signal of the light reception means, and a retiming circuit for retiming the output signal of the light reception means based on the clock signal produced by the PLL circuit, the PLL circuit including an oscillator for generating an oscillation frequency signal having a variable oscillation frequency, a signal generation circuit for generating, based on the oscillation frequency signal of the oscillator, a first signal having a phase same as that of the oscillation frequency signal, a second signal having a fixed phase difference from the first signal, and a third signal having a phase difference smaller than the phase difference between the first and second signals from the first signal, a phase detection circuit for comparing the phases of the third signal generated by the signal generation circuit and an input signal and outputting, based on a result of the comparison, a first phase control signal for advancing the phase of the oscillation frequency signal of the oscillator or a second phase control signal for delaying the phase of the oscillation frequency signal of the oscillator, and a frequency detection circuit for fetching the first and second signals generated by the signal generation circuit in synchronism with the input signal and outputting, based on the fetched signals, a first frequency control signal for raising the frequency of the oscillation frequency signal of the oscillator or a second frequency control signal for lowering the frequency of the oscillation frequency signal of the oscillator.
In the PLL circuit and the optical communication reception apparatus, the signal generation circuit generates, based on the oscillation frequency signal of the oscillator, a first signal having a phase same as that of the oscillation frequency signal, a second signal having a fixed phase difference from the first signal, and a third signal having a phase difference smaller than the phase difference between the first and second signals from the first signal, and the phase detection circuit performs phase control based on the phase difference between the third signal and the input signal. Consequently, a changing point of the third signal is set not to a changing point of the input signal but to a central portion of the pulse waveform. Consequently, the frequency detection circuit has an improved withstanding property against a metastable state which appears when the duty ratio of the input signal varies at a fetching timing of the first or second signal when the oscillation frequency is in the proximity of a particular frequency to which the oscillator is locked. Accordingly, even if the duty ratio of the input signal changes, the convergence time required for frequency detection of the frequency detection circuit is short and a malfunction with the control signal of the frequency detection circuit is less likely to occur. Therefore, operation of the entire PLL circuit is stabilized.
The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements denoted by like reference symbols.